1. Field of the Invention
The present invention relates to a semiconductor device that includes an oxide dielectric and a method for manufacturing the same, particularly (i) the surrounding structure of a local interconnection that electrically interconnects memory cells that include a metal oxide dielectric film and a method for manufacturing the same, and (ii) a semiconductor memory device that includes the surrounding structure of the local interconnection and a method for manufacturing the same.
2. Background of the Related Art
In general, interconnections used in a semiconductor device can be classified as a global interconnection and a local interconnection. An electrical connection over great distance is provided by a global interconnection. Therefore, a global interconnection is generally composed of a conductive material having a low resistance rate in order to reduce wiring delay. On the other hand, an electrical connection over short distance is provided by a local interconnection, in contrast to the above described global interconnection. Because of this, a local interconnection has a lower level of demand for reducing wiring delay compared to the global interconnection. Therefore, the local interconnection can be composed of a conductive material having a resistance rate that is higher than that of the global interconnection.
The above described heretofore known points are hereinafter explained by using a semiconductor memory device as an example. The semiconductor memory device includes a two-dimensional matrix array of a plurality of memory cells. In addition, each memory cell is comprised of at least a capacitor and a switching transistor. Therefore, a memory cell array of a semiconductor memory device has a plurality of capacitors. It is preferable to increase the number of memory cells because storage capacity is increased by the increased number of memory cells. However, problems related to the wiring delay tend to be caused by the increase in the number of memory cells.
The amount of the wiring delay is increased by the increase in the capacitance connected to one wiring. In particular, when numerous capacitors are connected to one global interconnection and the total capacitance connected to the global interconnection grows large, a large wiring delay tends to be caused in the global interconnection. Therefore, the local interconnection that electrically connects a plurality of capacitors located within a local region of a memory cell is generally provided. Thus, the capacitance connected to the global interconnection is lowered by connecting the local interconnection to the global interconnection through a switching transistor. This structure makes it possible for a semiconductor memory device to have high speed operation properties.
The distance of the local interconnection is shorter than that of the global interconnection. Therefore, the demand for lowering the resistance rate of conductive material composed of the local interconnection is lower than that of the global interconnection. For example, the global interconnection can be composed of aluminum (Al). On the other hand, the local interconnection can be composed of titanium nitride (TiN). Japan Patent Application Publication JP-A-11-54716 (especially paragraph number 0035 and FIG. 13) discloses a local interconnection composed of titanium nitride (TiN).
Recently, demands for increasing the degree of integration of the above described memory cell array have been increasing. In order to increase the degree of integration of the memory cell array, technologies in which the capacitor obtains high capacitance and each memory cell is miniaturized are in demand. It is widely known that metal oxide ferroelectrics or metal oxide high dielectrics are used as a capacitor dielectric comprising a capacitor in response to these demands.
On the other hand, it is also well known that the ferroelectric properties of the metal oxide ferroelectrics or the high dielectric properties of metal oxide high dielectrics are deteriorated by means of the reduction of the metal oxide ferroelectrics or the metal oxide high dielectrics. Specifically, reduction reactions are caused between hydrogen and the metal oxide ferroelectrics or the metal oxide high dielectrics, and thus the ferroelectric properties or the high dielectric properties are deteriorated. An upper electrode of a capacitor having a capacitor dielectric comprised of the metal oxide ferroelectrics or the metal oxide high dielectrics is connected to an interconnection layer through a contact hole. In general, after the interconnection layer is formed, an interlayer insulating film is formed above a capacitor and a conductive contact plug is formed in a contact hole that is formed in an interlayer insulation film with the chemical vapor deposition method (the CVD method). In this step, in which the CVD method is conducted, hydrogen that functions as the reducing agent is generated. In other words, hydrogen that functions as the reducing agent is generated in a manufacturing step, such as a step in which the CVD method is conducted, after an interconnection layer that has a contact with the upper electrode of the capacitor is formed.
However, the above described interconnection layer having a contact with the upper electrode is generally comprised of a conductive hydrogen permeable conductive substance, such as titanium nitride (TiN) and aluminum (Al). In addition, the above described upper electrode is comprised of a conductive hydrogen-permeable substance. Therefore, hydrogen penetrates into a capacitor dielectric through the interconnection layer and the upper electrode in a contact hole. Thus, reduction reactions are generated between hydrogen and the metal oxide ferroelectric or the metal oxide high dielectric. As a result, there is a possibility that the ferroelectric properties or the high dielectric properties of the capacitor dielectric will deteriorate. This deterioration makes it difficult for a capacitor to obtain high capacitance. Consequently, it becomes difficult for each memory cell to be miniaturized and further difficult for the degree of integration of the memory cell array to be increased.